This invention relates to semiconductor integrated circuit fabrication techniques, and more particularly, to techniques for planarizing wafer surfaces during the fabrication of self-aligned integrated circuit well structures.
As integrated circuits become more complex, there is a need to produce circuits of ever-increasing size and density. However, fabricating more dense integrated circuits requires that the critical dimensions of the various integrated circuit components be reduced. As the dimensions of circuit components on a wafer are reduced, the topography of the surface of the wafer can become highly non-planar. However, such non-planar wafer topographies are undesirable, because non-planar wafer structures can make circuit fabrication difficult. For example, it is difficult to pattern non-planar layers during circuit fabrication due to the depth-of-field limitations of available photolithography tools.
Although techniques exist for maintaining a relatively planarized wafer surface during circuit fabrication, such techniques generally involve numerous additional processing steps and do not allow the formation of self-aligned structures. Self-aligned structures are desirable, because they can be formed using less wafer surface area than equivalent structures which are not self-aligned.
It is therefore an object of the present invention to provide an improved method of fabricating semiconductor integrated circuits.
It is a further object of the present invention to provide a method of fabricating a planar self-aligned integrated circuit structure suitable for use in forming complementary metal-oxide-semiconductor integrated circuits.